Add interface for application register barriers inside the core

When the DR core performs certain "mangling" operations (application transformations required for core operation), it needs to read application register values. This can conflict with drreg and clients in general who may be storing app values in memory temporarily. This issue is asking for some kind of interface where the core can interact with drreg and clients to request a barrier where all values need to be in registers.

Today, for rseq (#2350 (closed)), such a barrier is assumed to be in place at the start and end of blocks. drreg obeys that today. In the future we may want to support longer-range optimizations and trace optimizations, however.

This issue also covers documenting these implicit barriers.